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 ________________________________________________________________ maxim integrated products 1 15 16 14 13 6 5 7 drain fb 8 drain pgnd cko source 12 reset 4 12 11 9 bst/vdd en v l v+ bypass osc max5088 comp sgnd 3 10 sync ep* *exposed pad. thin qfn 5mm x 5mm top view + ``````````````````````````````` [ m|? ``````````````````````````````` ? g? 19-3944; rev 1; 5/06 ta5nbyjnu+^at ?|ianbyjny !i|@?|?j
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?  part temp range pin- package pkg code max5088 ate+ -40c to +125c 16 tqfn t1655-2 max5089 ate+ -40c to +125c 16 tqfn t1655-2 ``````````````````````````````` ?o? part configuration features max5088ate nonsynchronous buck reset output, clock output max5089ate synchronous buck pgood output, synchronous fet driver + -,? v? - ? e?
nby61990nby619: 3/3ni{3b ]1ot
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 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v+ = v l = 5v or v+ = 5.5v to 23v, v en = 5v, t a = t j = -40c to +125c, unless otherwise noted. circuits of figures 5 and 6. typical values are at t a = t j = +25c.) (note 1) stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to pgnd............................................................-0.3v to +25v bst/vdd, drain to sgnd ....................................-0.3v to +30v sgnd to pgnd .....................................................-0.3v to +0.3v bst/vdd to source...............................................-0.3v to +6v source to sgnd..................................................-0.6v to +25v source or drain maximum peak current...............5a for 1ms v l to sgnd ................-0.3v to the lower of +6v and (v+ + 0.3v) sync, en, dl, cko, osc, comp, fb to sgnd...............................................-0.3v to (v l + 0.3v) bypass, cko, osc, comp, fb, en, sync, reset, pgood maximum input current .................................50ma reset , pgood to sgnd ........................................-0.3v to +6v bypass to sgnd..................................................-0.3v to +2.2v v l and bypass short-circuit duration to sgnd ......continuous continuous power dissipation* (t a = +70c) 16-pin tqfn (derate 33mw/c above +70c) ..........2666mw package thermal resistance (junction to case) ............1.7c/w operating temperature range .........................-40c to +125c junction temperature range ............................-65c to +150c storage temperature range .............................-65c to +150c lead temperature (soldering, 10s) .................................+300c *as per jedec51 standard (multilayer board). parameter symbol conditions min typ max units system specifications 5.5 23.0 v input voltage range v+ v+ = v l 4.5 5.5 v v+ operating supply current i q v+ = 12v, v fb = 0.8v r osc = 10k ?, , ,, ,, , ,, , , ,, , , ,
nby61990nby619: 3/3ni{3b ]1ot
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 _______________________________________________________________________________________ 3 electrical characteristics (continued) (v+ = v l = 5v or v+ = 5.5v to 23v, v en = 5v, t a = t j = -40c to +125c, unless otherwise noted. circuits of figures 5 and 6. typical values are at t a = t j = +25c.) (note 1) parameter symbol conditions min typ max units soft-start digital soft-start period internal 6-bit dac 4096 clock periods soft-start steps 64 steps error amplifier (fb and comp) fb to comp transconductance g m 1.20 1.8 2.75 ms fb input bias current i fb 250 na fb input voltage set point v fb 0.5940 0.601 0.6095 v comp sink-and-source current capability i comp 100 150 a internal mosfets on-resistance n-channel power mosfet r on v+ = v l = 5.2v, i sink = 100ma 0.150 0.302  leakage current i leak v en = 0v, v drain = 23v, source = pgnd 20 a minimum output current i out v out = 3.3v, v+ = 12v (note 2) 2 a current limit i limit 2.2 2.8 3.5 a on-resistance internal low-side switch r onlsw i switch = 50ma, v+ = v l = 5.2v 20 38  synchronous rectifier driver (dl) (max5089 only) on-resistance nmos r ondln i sink = 0.1a 1 6.7  on-resistance pmos r ondlp i source = 0.1a 1.9 11.1  peak sink current i idl_sink 1a peak source current i idl_source 0.75 a oscillator (osc)/synchronization (sync)/clock output (cko) (max5088 only) clock output-high level v ckoh v l = 5.2v, i source = 5ma 3.54 v clock output-low level v ckol v l = 5.2v, i sink = 5ma 0.4 v r osc = 5.62k  1900 2100 2400 r osc = 41.2k  275 312 350 switching frequency f sw v+ = v l = 5.2v r osc = 10k  1130 1250 1380 khz minimum controllable on-time t on_min 120 ns max5088 82 87.5 maximum duty cycle d max f sw = 2.2mhz max5089 82 87.5 %
nby61990nby619: 3/3ni{3b ]1ot
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 4 _______________________________________________________________________________________ electrical characteristics (continued) (v+ = v l = 5v or v+ = 5.5v to 23v, v en = 5v, t a = t j = -40c to +125c, unless otherwise noted. circuits of figures 5 and 6. typical values are at t a = t j = +25c.) (note 1) parameter symbol conditions min typ max units sync frequency range (note 3) f sync 200 2200 khz sync input to source rising- edge phase delay (note 4) sync phase r osc = 10k reset et e e reset t t t t t t t t reset reset t r reset s reset e reset terst ts t s t ts s s ssre sre reset t t
nby61990nby619: 3/3ni{3b ]1ot
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 _______________________________________________________________________________________ 5 max5088 buck efficiency vs. output current (v in = 5v, f sw = 2.2mhz) max508889 01 output current (a) efficiency () 2000 1500 1000 500 10 20 30 40 50 60 70 80 90 0 0 2500 3.3v 2.5v max5088 buck efficiency vs. output current (v in = 12v, f sw = 2.2mhz) max508889 02 output current (a) efficiency () 2000 1500 500 1000 10 20 30 40 60 50 70 80 0 0 2500 3.3v 2.5v max5088 buck efficiency vs. output current (v in = 16v, f sw = 2.2mhz) max508889 03 output current (a) efficiency () 2000 1500 1000 500 10 20 30 40 50 60 70 0 0 2500 3.3v max5089 synchronous efficiency vs. output current (v in = 12v, f sw = 330khz, l = 15 h) max508889 04 output current (a) efficiency () 2000 1500 1000 500 55 60 65 70 75 80 85 90 95 50 0 2500 3.3v 2.5v 1.2v max5089 synchronous efficiency vs. output current (v in = 12v, f sw = 2.2mhz, l = 4.7 h) max508889 05 output current (a) efficiency () 2000 1500 1000 500 35 40 45 50 55 60 65 70 75 80 30 0 2500 3.3v max5089 output voltage vs. output current (v in = 12v, v out = 3.3v, f sw = 2.2mhz) max508889 06 output current (a) output voltage (v) 2000 1500 1000 500 3.285 3.290 3.295 3.300 3.305 3.310 3.315 3.280 0 v l output voltage vs. switching frequency max508889 07 switching frequency (khz) v l (v) 2100 1600 600 1100 5.155 5.160 5.165 5.170 5.180 5.175 5.185 5.190 5.150 100 v in = 23v v in = 5.5v v (v = v l = 5.2v, t a = 25c, fs 5 6, ss s .)
nby61990nby619: 3/3ni{3b ]1ot
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 6 _______________________________________________________________________________________ ``````````````````````````````````````````````````````````````` `````?o ?+v)?? (v+ = v l = 5.2v, t a = +25c, figures 5 and 6, unless otherwise noted.) max5089 v l dropout voltage vs. switching frequency max508889 08 switching frequency (khz) v l dropout voltage (v) 2100 1600 600 1100 0.050 0.100 0.150 0.200 0.300 0.250 0.350 0.400 0 100 v = 5.5v v = 5.25v v = 5v switching frequency vs. r osc max508889 09 resistance (k ) () switching frequency vs. temperature max508889 10 temperature ( ) () = = = = max5089 line-transient response (i out = 1a, v in step = 14v to 21v) max508889 11 100 = max5089 load-transient response (i out = 0.5a to 2a) max508889 13 20 = = max5089 load-transient response (i out = 0.2a to 1a) max508889 12 20 = = max5089 soft-start and shutdown (no load) max508889 14 1sv v out 1vv 0v 0v 5vv v en v in = 12v
nby61990nby619: 3/3ni{3b ]1ot
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 _______________________________________________________________________________________ 7 ``````````````````````````````````````````````````````````````` `````?o ?+v)?? (v+ = v l = 5.2v, t a = +25c, figures 5 and 6, unless otherwise noted.) max5089 soft-start and shutdown (i out = 2a) max508889 15 1sv v out 1vv 0v 0v 5vv v en v in = 12v v in startup waveform (en connected to v l ) max508889 16 1sv v en 5vv v out 2vv v pgood 5vv v in 10vv reset timeout max508889 17 40sv 10vv v in v en v out v reset 5vv 5vv 2vv max5088 externally synchronized switching waveform max508889 18 100sv 5vv 5vv 10vv 0v 0v 0v v sync v clkout v source v out 500vv shutdown current vs. temperature max508889 19 temperature ( ) ( ) switching supply current (i sw ) vs. temperature max508889 20 temperature ( ) () = = = = = = current limit vs. temperature max508889 21 temperature ( ) () = = =
nby61990nby619: 3/3ni{3b ]1ot
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 8 _______________________________________________________________________________________ ``````````````````````````````````````````````````````````````` ``````````````` [ m? 1, 2 drain 3 comp 4fb 5osc 6 bypass 7v+ 8v l cko 9 dl 10 sgnd 11 pgnd 12 source 13 sync reset 14 pgood 15 bst/vdd 16 en ?ep [ m a ? ] ? hnptgfu| '
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nby61990nby619: 3/3ni{3b ]1ot
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 _______________________________________________________________________________________ 9 ldo oscillator v+ drain sync 2v 1v q r 4-pulse skip r sense v ref = 0.6v 0.92 x v ref 200mv 180ms delay v l = 5.2v bst/vdd v l source pgnd fb comp reset q adaptive bbm n2 200m ? ???
nby61990nby619: 3/3ni{3b ]1ot
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 10 ______________________________________________________________________________________ ldo oscillator v+ drain sync 2v 1v q r 4-pulse skip r sense v ref = 0.6v 0.92 x v ref 200mv v l = 5.2v bst/vdd v l source pgnd dl vl fb comp pgood q adaptive bbm n2 200m ? ???
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nby61990nby619: 3/3ni{3b ]1ot
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 18 ______________________________________________________________________________________ v ref v out r1 comp r2 r f c f c cf g m d4/! jjow?? e v ref v out r1 comp c cf r f c f r2 g m r a c a d5/! jjjow?? e
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 20 ______________________________________________________________________________________ max5088 9 12 15 r7 15 + + ? ??
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 ______________________________________________________________________________________ 21 max5089 1 2 5 6 4 n1 3 r6 4.7 + + ? ??
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 22 ______________________________________________________________________________________ v+ drain output1 c in v in source clkout master sync sync clkout (master) source (master) source (slave) clkin duty cycle = 50% v+ drain source slave sync output2 sync phase clkout phase d8/! 4[t
 15 16 14 13 6 5 7 drain fb 8 drain pgnd dl source 1 + 2 pgood 4 12 11 9 bst/vdd en v l v+ bypass osc max5089 comp sgnd 3 10 sync thin qfn 5mm x 5mm top view ep* *exposed pad. ```````````````````````````` [ m|?)?* ````````````````````````````````g? process: bicmos
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 ______________________________________________________________________________________ 23 ``````````````````````````````````````````````````````````````` ````````````` v?g? ( ) qfn thin.eps
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